An example of conventional logic circuits comprising CMOS's is shown in FIG. 1. This circuit is four-input NAND circuit.
This logic circuit includes P-type MOS field effect transistors (hereinafter referred to as PMOSFET's) 81, 82, 83 and 84 having their source-drain conduction paths connected in parallel between an output terminal 89 of the circuit and a voltage supply VDD. The gates of these PMOSFET's 81-84 receive input signals A, B, C, and D, respectively. Between the output terminal 89 and a ground line, the drain-source conduction paths of N-type MOS field effect transistors (hereinafter referred to as NMOSFET's) 85, 86, 87 and 88 are connected in series. The gates of these NMOSFET's 85-88 also receive the input signals A, B, C, and D, respectively. The input signals A, B, C, and D assume either a higher potential (e.g. VDD) or a lower potential (e.g. ground potential).
In FIG. 1, when at least one of the input signals A, B, C, and D is at the lower potential, at least one of PMOSFET's 81-84 is conductive and, therefore, the output terminal 89 receives current from the voltage supply VDD. At the same time, at least one of the NMOSFET's 85-88 is non-conductive, and, therefore, no current will flow from the output terminal 89 to the ground line. Thus, the output terminal 89 is charged through at least one of the PMOSFET's so that its potential rises. If all of the input signals A, B, C, and D are at the high potential, all of the PMOSFET's 81-84 are non-conductive, whereas all of the NMOSFET's 85-88 are conductive. Accordingly charge stored at the output terminal 89 is discharged through the NMOSFET's 85-88 to the ground line and its potential decreases. In other words, the output of this four-input NAND circuit is expressed as (A.multidot.B.multidot.C.multidot.D).
An example of conventional four-input NAND circuit comprising a combination of CMOSFET's and bipolar transistors is shown in FIG. 2. This circuit was disclosed at 1990 Symposium on VLSI Circuits held in Honolulu, Jun. 7-9, 1990 by G. Boudon et al. (see pages 87-88 of Digest of Technical Papers). Different from the circuit shown in FIG. 1, this circuit includes NPN bipolar transistors 95, 96, 97 and 98 having their collector-emitter conduction paths connected in parallel with each other between an output terminal 9K and a voltage supply VDD. More specifically, the collectors of the transistors 95-98 are connected to the voltage supply VDD and the emitters are connected to the output terminal 9K. The bases of the bipolar transistors 95-98 receive input signals A, B, C and D after they are inverted by CMOS inverters 91, 92, 93 and 94, respectively. An NPN bipolar transistor 9J has its collector connected to the output terminal 9K and has its emitter connected to a grounded line. Source-drain conduction paths of NMOSFET's 99, 9E, 9F and 9G are connected in series between the output terminal 9K and the base of the transistor 9J. The gates of the NMOSFET's 99, 9E, 9F and 9G receive the input signals A, B, C and D, respectively. Between the base of the transistor 9J and ground, the source-drain conduction path of an NMOSFET 9H is connected. The gate of the NMOSFET 9H receives a voltage developed at the output terminal 9K.
In FIG. 2, when at least one of the input signals A, C, and D is at the low potential, at least one of the inverters 91-94 develops an output at the high potential so that a base current is supplied to the bipolar transistor connected to that inverter to render that bipolar transistor conductive. Then the output terminal 9K is charged through the now conducting bipolar transistor from the voltage supply VDD so that its potential rises. When all of the input signals A, B, C, and D are at the high voltage, the outputs of all of the inverters 91-94 are at the low potential. This causes all of the bipolar transistors 95-98 to become non-conductive, while all of the NMOSFET's 99-9G are rendered conductive to provide a base current to the bipolar transistor 9J. This, in turn, causes the bipolar transistor 9J to become conductive so as to discharge the output terminal 9K through the transistors 9J, and, therefore, the potential at the output terminal 9K decreases. In other words, the output of the four-input NAND circuit shown in FIG. 2, similar to the four-input NAND circuit of FIG. 1, is expressed as (A.multidot.B.multidot.C.multidot.D). The NMOSFET 9H is connected between the base of the bipolar transistor 9J and ground for the following reason. When the output terminal 9K changes from the low potential to the high potential, it is necessary to make the conducting bipolar transistor 9J non-conductive rapidly. If it takes a long time for the bipolar transistor 9J to change to the non-conductive state, current to charge the output terminal 9K would flow through the bipolar transistor 9J to ground, which increases consumed current and also time necessary for the output terminal 9K to changed from low to high potentials. In order to prevent this from occurring, when the output terminal 9K changes from the low potential to the high potential, such change is used to render the NMOSFET 9H conductive to draw charge stored on the base of the transistor 9J into ground so that the bipolar transistor 9J can rapidly turned off.
In the NAND circuit arrangement shown in FIG. 1, for an increased number of input signals, the number of NMOSFET's to be connected between the output terminal 89 and ground must be increased. The particular circuit shown in FIG. 1, because the number of input lines is four, the number of the NMSOFET's is four. However, if the number of input lines is increased to, for example, eight, the number of the NMOSFET's must be also doubled to eight. Increase in number of serially connected NMOSFET's means increase in the equivalent resistance between the output terminal 89 and ground exhibited when all of these NMOSFET's become conductive. (This equivalent resistance is equal to the sum of the ON-resistances of all of the NMOSFET's.)
The increase of the equivalent resistance causes current flowing from the output terminal 89 to ground to decrease. Consequently, as the number of input signals to the NAND circuit of FIG. 1 increases, the speed at which the output terminal 89 changes from its high potential to the low potential decreases. It may be possible to improve the changing speed by reducing the ON-resistances of the respective NMOSFET's. It, however, requires to increase the size of each of the NMOSFET's, which could be accompanied by increase of the input capacitance. This means increase of load to the stage preceding the NAND circuit which drives the NAND circuit.
Another problem exists. When, for example, the output of the NAND circuit of FIG. 1 is used as a common input to a number of logic circuits, the load capacitance on the output terminal 89 increases so that the time for charging and discharging the output terminal 89 increases. In order to avoid it, the size of each MOSFET may be increased to make use a larger drive current. However, as aforementioned, this increases the input capacitance of this NAND circuit, which means that the load on the preceding circuit increases. In place of increasing the sizes of the MOS transistors, the arrangement shown in FIG. 2 employs bipolar transistors to increase a drive current. In the arrangement shown in FIG. 2, the bipolar transistors 95, 96, 97 and 98 are driven by being supplied with their respective base currents from the CMOS inverters 91, 92, 93 and 94, respectively, and the bipolar transistor 9J is driven by being supplied with its base current from the NMOSFET's 99, 9E, 9F and 9G. Accordingly, the output terminal 9K is charged and discharged by a current flowing through a currently conducting MOS amplified by the bipolar transistor by its current amplification factor. This current amplification factor is on the order of 100, and, therefore, even when the output load capacitance is large, the output potential can rapidly rise or fall.
Although the arrangement of FIG. 2 has an advantage that even when the load capacitance at the output terminal 9K is large, the terminal 9K can be rapidly charged or discharged, it had a disadvantage that the number of constituent components increases. Specifically, in comparison with the CMOS circuit of FIG. 1, the number of NMOSFET's is doubled from 4 to 8. This increases a corresponding increase of not only the area occupied by the NMOSFET's but also input capacitance. Furthermore, since the NMOSFET's 99, 9E, 9F and 9G which drive the bipolar transistor 9J are connected in series, the same problem of degradation of the output potential rising and fall characteristic as in the arrangement of FIG. 1 is still present.
The above-described problems are solved by the present invention. According to the present invention, a logic circuit is provided, which has a time of transition from a high potential to a low potential that is less dependent on the number of input signals, and which can comprise a small number of circuit components.